1. Field of the Invention
The present application relates generally to a design structure and more specifically, to a design structure for a phase locked loop (PLL) circuit that provides a desired duty cycle while allowing for the removal of the PLL's pre-scaler.
2. Background of the Invention
A phase locked loop (PLL) is a closed loop feedback control system that generates an output signal in relation to the frequency and phase of an input, or reference, signal. The PLL automatically responds to the frequency and phase of the input signal by raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. PLLs are widely used in computing devices, telecommunications systems, radio systems, and other electronic applications where it is desired to stabilize a generated signal or to detect signals in the presence of noise. Since an integrated circuit can hold a complete PLL, the use of PLLs in modern electronic devices is widespread.
FIG. 1 is an exemplary block diagram of a conventional resistance/capacitance (RC) phase locked loop (PLL) circuit. As shown in FIG. 1, the conventional RC PLL circuit 100 includes a receiver (RX) 110 coupled to a phase frequency detector (PFD) 115 which is in turn coupled to a charge pump (CP) 120. A reference current signal from a reference current circuit (IREF) 125 is provided as an input to the charge pump 120 along with a control input, via a PMP bus for example, specifying the setting of the charge pump 120. The control input, which is set by a configuration register or is hard-wired into the circuit, sets the peak current for the charge pump 120. The charge pump is coupled to a resistor (R2) 130 and capacitor (CFILT) 135 which together constitute a resistance/capacitance (RC) filter 140 (also sometimes referred to as a “loop filter”). The RC filter 140 is coupled to a voltage controlled oscillator (VCO) 145 which in turn is coupled to a buffer 147 and a first divider 150. A feedback path is provided back to the input of the PFD 115 via a second divider 155.
The conventional RC PLL circuit 100 operates in a manner generally known in the art. That is, assuming the RC PLL circuit 100 is used for generating a core clock signal for a processor or other integrated circuit device, a reference clock signal is provided to the RC PLL circuit 100 via receiver 110. Preferably, the input to the receiver 110 is coupled to an external reference clock while the output of the first divider 150 is coupled to a clock input of a processor or other integrated circuit device. This reference clock signal is input to the phase frequency detector 115 which also receives as an input a feedback clock signal from the second divider 155, which divides the feedback signal from the first divider 150 by a programmable amount. The phase frequency detector 115 compares the feedback clock signal from the second divider 155 and detects a difference in phase and frequency between the reference clock signal and the feedback clock signal. The phase frequency detector 115 then generates an “up” or “down” control signal based on whether the feedback clock signal frequency is lagging or leading the reference clock signal frequency. These “up” or “down” control signals determine whether the VCO 145 needs to operate at a higher or lower frequency, respectively.
The PFD 115 outputs these “up” and “down” signals to the charge pump 120. If the charge pump 120 receives an “up” control signal, current is driven into the RC filter 140. Conversely, if the charge pump 120 receives a “down” control signal, current is drawn from the RC filter 140. The RC filter 140 converts these control signals into a control voltage that is used to bias the VCO 145. Based on the control voltage, the VCO 145 oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock signal. If the PFD 1 15 produces an “up” control signal, then the VCO 145 frequency is increased. If the PFD 115 produces a “down” control signal, then the VCO 145 frequency is decreased. The VCO 145 stabilizes once the reference clock signal and the feedback clock signal have the same phase and frequency. When the reference clock signal and the feedback clock signal are aligned, the PLL circuit 100 is considered locked.
The RC filter 140 operates to filter out jitter from the charge pump 120 output and to prevent voltage over-shoot. Thus, the operation of the RC filter 140 affects the damping factor of the PLL circuit 100. The first and second dividers 150 and 155 operate to increase the VCO 145 frequency above the reference frequency of the reference clock signal. That is, the VCO 145 frequency is equal to a multiple of the reference clock signal frequency which may then be reduced by the divider circuits 150 and 155.
The first divider 150 is sometimes implemented as a divide-by-2 VCO pre-scaler circuit whose purposes is to provide a 50% duty cycle clock output signal to the processor or integrated circuit device. As is generally known in the art, a divide-by-2 VCO pre-scaler circuit provides a 50% duty cycle output signal regardless of the duty cycle of the input signal to the divide-by-2 circuit. Unfortunately, the divide-by-2 VCO pre-scaler wastes half of the available PLL frequency range. For example, in 90 nm silicon on insulator (SOI) process, the PLL has the capacity to generate frequency ranges that are in excess of 10 GHz. Setting the VCO pre-scaler to a divide-by-2 VCO pre-scaler in order to get a 50% duty cycle, essentially reduces the available frequency range by half, i.e. to 5 GHz. In current applications, such wastage is not generally a problem since most modern microprocessors have operating frequencies that are less than 5 GHz. However, for future applications, it is conceivable that all of the available frequency range would need to be exploited. Hence, it would be desirable to be able to remove the divide-by-2 VCO pre-scaler while at the same time providing a good duty cycle from the VCO.
In some implementations of a PLL, the VCO pre-scaler is removed and a duty cycle correction (DCC) circuit is introduced at the output of the PLL. Such an example PLL is illustrated in FIG. 2. The DCC circuit 210 allows the output duty cycle of the PLL to be controlled. However, this control comes with a penalty of added latency. Furthermore, since the PLL has no control over the input to the DCC circuit 210, once the signal switch from the VCO gets below a threshold, the DCC circuit 210 will no longer be functional. Such a scenario can occur, for example, if there was process skew that made the N type field effect transistors (NFETs) of the VCO stronger than the P type field effect transistors (PFETs) of the VCO, and vice versa.